Conventionally, for quality judgment of a circuit including analog circuits such as an AD conversion circuit and a DA conversion circuit, an evaluation circuit needs to be provided in advance in the circuit so as to carry out a test for evaluating the performance of the circuit. However, the evaluation circuit thus provided causes property change of each of the analog circuits, and requires an external high accuracy evaluation apparatus.
In light of such problems, a technique disclosed in Japanese Unexamined Patent Publication Tokukaihei 08-68833/1996 (published on Mar. 12, 1996; hereinafter, referred to as “Patent document 1”) makes it possible to acquire a property of the DA conversion circuit, for example, in the following manner. That is, the circuit is arranged such that an output terminal of the DA conversion circuit is connectable to an input terminal of the AD conversion circuit, and test data is used as reference data.
Further, proposed in each of Japanese Unexamined Patent Publication Tokukaihei 05-297061/1993 (published on Nov. 12, 1993; hereinafter, referred to as “Patent document 2”), Japanese Unexamined Patent Publication Tokukai 2004-48383/2004 (published on Feb. 12, 2004; hereinafter referred to as “Patent document 3”), and the like is a method using an FFT (Fast Fourier Transform) circuit provided in addition to the DA conversion circuit and the AD conversion circuit. A specific example of the FFT circuit is a DSP (digital signal processing) circuit. Specifically, the FFT circuit thus provided is used to acquire respective properties of the DA conversion circuit and the AD conversion circuit, and the properties thus acquired are automatically corrected, and the properties thus corrected are used for the evaluation.
The technique of the patent document 1 requires a highly accurate analog signal for the test of the AD conversion circuit, and merely allows acquirement of an output result obtained through two circuits. Therefore, it is difficult to distinguish which one of the two circuits caused an obtained error. On the other hand, the technique proposed in each of Patent documents 2 and 3 etc., requires the FFT circuit, so that the test requires expensive cost.
Further, such a circuit including the analog circuits generally suffers from (i) a problem in a relation between high accuracy and low power consumption, and (ii) a problem in a relation between a margin in designing and the low power consumption. The following explains the problems.
A specific example of the circuit including the analog circuits is the AD conversion circuit for converting an analog input value into a digital value. Described fully in “A 10 b, 20 Msample/s, 35 mW Pipeline A/D Converter”, IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 30, NO. 3, MARCH 1995 (hereinafter, referred to as “Non-patent document 1”) is a pipeline AD conversion circuit for carrying out high speed AD conversion in a plurality of stages. FIG. 11 illustrates a structure of such a pipeline AD conversion circuit 100. The pipeline AD conversion circuit 100 includes a plurality of stages (STAGE 1 through STAGE N) 106 through 109. The k-th one (STAGE k; k=1 through N−1) of the stages includes a sub AD converter 101, a sub DA converter 102, an adder 103, and an n-time amplifier 104. The sub AD converter 101 carries out AD conversion with respect to an input signal Vres(k−1), and outputs a digital value Dk. The sub DA converter 102 converts (i) the digital value DK obtained as the result of the AD conversion carried out by the sub AD converter 101, into (ii) an analog value. The adder 103 adds (i) the output of the sub DA converter 102, to (ii) the input signal Vres(k−1). The n-time amplifier 104 amplifies (multiplies) the addition result by n times, and carries out an analog output thereof. Described here is an example in which the addition result is multiplied by 2. Further, hereinafter in the present application, this multiple number is referred to as “gain”. Respective functions of the adder 103 and such a two-time amplifier 104 are realized by a two-time amplifier circuit 111. The two-time amplifier circuit 111 sends an analog signal Vres(k) to a next stage. Moreover, the pipeline AD conversion circuit 100 further includes a bias voltage generation circuit 105 for generating and sending a bias voltage Vb to the n-time amplifier 104. The application of the bias voltage Vb causes the n-time amplifier 104 to operate.
The first stage 106 outputs a digital output D1, which serves as an MSB (Most Significant Bit). The two-time amplifier circuit 111 in the stage 107 coming just after the first stage 106 amplifies, by 2, a difference between an input signal Vres2 and the digital value D1. Accordingly, the stage 107 outputs a digital output D2 whose weight is the half of that of the MSB. Each of stages coming after the stage 107 until the last stage (Stage N) 109 outputs a digital output, and sends, to a next stage, an analog signal obtained by multiplying, by two, a difference between (i) an analog signal received by the stage and (ii) the digital output sent from the stage. In the structure of this case, the last stage (STAGE N) does not need to send a signal to a next stage, so that the last stage is merely made up of the sub AD converter 101. The N-number of stages required according to required accuracy (bit number) N are connected to one another in the form of a pipeline as shown in FIG. 11, thus constituting the pipeline AD conversion circuit 100. Further, the respective digital outputs from the stages are combined by an error correction circuit 110, and the error correction circuit 110 outputs the combined digital output as a final digital output Dout sent from the pipeline AD conversion circuit 100. The pipeline AD conversion circuit 100 carries out the process in the pipeline manner as such, so that each of the stages can operate at an operation speed equal to conversion speed. Therefore, the conversion speed, the accuracy, and the current consumption are excellently balanced in the pipeline AD conversion circuit 100, so that the pipeline AD conversion circuit 100 is most frequently used as a 10-bit AD conversion circuit through a 12-bit AD conversion circuit, each of which deals with up to several ten M samples.
Explained next is a structure of the switched capacitor circuit (n-time amplifier circuit) 111 realizing the respective functions of the adder 103 and the n-time amplifier 104 of each stage. In this structure example, the gain is two, so that the switched capacitor circuit 111 serves as a two-time amplifier circuit 111. Such a two-time amplifier circuit 111 is so arranged as to amplify, by two, the difference between the input signal Vres(k−1) and the signal VDAC sent from the sub DA converter 102, and as to send the signal Vres(k) in the form of a differential output. Further, the two-time amplifier circuit 111 includes an amplifier 112; switches SW1, SW2, and SW3; and capacitors Cf and Cs. Note that, FIG. 11 illustrates only one of two circuits connected to the differential input terminals of the amplifier 112, and does not illustrate the other circuit connected thereto because the other circuit is provided symmetrically to the circuit. The amplifier 112 receives the aforementioned bias voltage Vb. Each of the capacitors Cf and Cs has an electrode connected to an input terminal of the amplifier 112. The switch SW1 switchably connects the other electrode of the capacitor Cf to one of (i) the input terminal for receiving the input signal Vres(k−1), and (ii) the output terminal of the amplifier 112. The switch SW2 switchably connects the other electrode of the capacitor Cs to one of (i) the input terminal for receiving the input signal Vres(k−1), and (ii) the input terminal for receiving the signal VDAC. The switch SW3 connects the input terminal of the amplifier 112 to an input terminal for receiving a reference voltage Vref, and disconnects the input terminal of the amplifier 112 from the input terminal for receiving the reference voltage Vref.
While the two-time amplifier circuit 111 thus arranged is in a mode of sampling the input signal Vres(k−1), the switch SW1 connects the other electrode of the capacitor Cf to the input terminal for receiving the input signal Vres(k−1). The switch SW2 connects the other electrode of the capacitor Cs to the input terminal for receiving the input signal Vres(k−1). The switch SW3 connects the input terminal of the amplifier 112 to the input terminal for receiving the reference voltage Vref. This causes each of the capacitors Cf and Cs to accumulate an electric charge determined by a difference between the voltage of the input signal Vres(k−1) and the reference voltage Vref.
On the other hand, while the two-time amplifier circuit 111 is in a hold mode of sending the output signal Vres(k), the switch SW1 connects the other electrode of the capacitor Cf to the output terminal of the amplifier 112. The switch SW2 connects the other electrode of the capacitor Cs to the input terminal for receiving the signal VDAC. The switch SW3 disconnects the input terminal of the amplifier 112 from the input terminal for receiving the reference voltage Vref. This allows retainment of the total electric charge accumulated in the respective electrodes of the capacitors Cf and Cs, and allows the input terminal of the amplifier 112 to receive a voltage determined by the signal VDA and the output voltage of the amplifier 112.
The following formula 1 expresses a relation between (i) the input to each stage including such a two-time amplifier circuit 111, and (ii) the output therefrom:Vres1=2·(Vres0−VDAC) VDAC=±0.5Vr,0  [Formula 1]
In consideration of a device property, the formula 1 is modified to the following formula 2:
                                                                        V                res1                            =                            ⁢                                                                    (                                          1                      +                                                                        C                          s                                                                          C                          f                                                                                      )                                    ·                                      (                                          1                                              1                        +                                                  1                          Af                                                                                      )                                    ·                                      (                                                                  V                        res0                                            -                                              V                        DAC                                                              )                                                  ⁢                                  V                  DAC                                                                                                                        =                                ⁢                                                      ±                    0.5                                    ⁢                  Vr                                            ,              0                                                          [                  Formula          ⁢                                          ⁢          2                ]            where “A” indicates a DC gain of the amplifier 112, and “f”indicates a feedback factor. The formula 2 allows no deviation of a ratio of the respective capacitances of the capacitors Cs and Cf. In other words, in accordance with the formula 2, the actual ratio of the capacitances of the capacitors Cs and Cf are equal to the ideal ratio of the capacitances of the capacitors Cs and Cf. In cases where “A”is infinite, the formula 2 is equal to the formula 1.
Each of FIG. 12(a) through FIG. 12(e) illustrates the relation between (i) the input voltage Vin (input signal Vres(k−1)) applied to the two-time amplifier circuit 111, and (ii) the output voltage Vout (output signal Vres(k)) from the two-time amplifier circuit 111. Specifically, FIG. 12(a) illustrates a designed input/output relation. In the designed input/output relation, when the bit value judgment result (the digital value Dk) sent from the sub AD converter 101 is 1, the two-time amplifier circuit 111 outputs a voltage obtained by multiplying, by two, a voltage obtained by subtracting a threshold value from the voltage received by the sub AD converter 101. On the other hand, when the bit value judgment result (the digital value Dk) is 0, the two-time amplifier circuit 111 outputs a voltage obtained by multiplying, by two, the voltage received by the sub AD converter 101. The output voltage Vout falls within a range from −Vref to +Vref. Further, an input voltage Vin equal to the threshold voltage is indicative of 0.
Each of FIG. 12(b) through FIG. 12(d) illustrates a case where the amplifier manufacture fluctuation causes the input/output relation to deviate from the ideal input/output relation. Specifically, FIG. 12(b) illustrates a case where the output voltage Vout falls within a range smaller than the foregoing range from −Vref to +Vref. FIG. 12(c) illustrates a case where: an electric charge irrelevant to the signal is accumulated, as an offset electric charge, in each of the capacitors Cf and Cs during the aforementioned sampling mode and the hold mode in each of which the electric charge is injected to the capacitors Cf and Cs, with the result that the output voltage Vout falls out of the foregoing range. FIG. 12(d) illustrates a case where the offset phenomenon causes the output voltage Vout to deviate from the target voltage corresponding to the input voltage Vin. The wording “offset phenomenon” refers to such a phenomenon that changes the threshold voltage with which a comparison device of the sub. AD converter 101 compares the input voltage Vin. This causes the comparison device to output a value determined in accordance with the threshold voltage thus changed from the original threshold value. FIG. 12(e) illustrates a case where the deviation of the ratio of the respective capacitances of the capacitors Cs and Cf causes the input/output relation to deviate from the ideal input/output relation.
In fact, degree of deviation of each capacitance of the capacitors Cs and Cf is in inverse proportion to the square root of each capacitance of the capacitors Cs and Cf. Therefore, in cases where the pipeline AD conversion circuit is applied to a 12 bit or greater high accuracy AD conversion circuit, the first stage needs to have a considerably large capacitance, and the amplifier 104 needs to have a considerably high DC gain A. This causes circuit area increase and electric current consumption increase. Therefore, it is difficult to use the pipeline structure directly for an application having limitation in electric current consumption such as a mobile phone. So, considered in each of “A 15 b, 1-Msample/s Digitally self-Calibrated Pipeline ADC”, IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 28, NO. 12, DECEMBER 1993 (hereinafter, referred to as “Non-patent document 2”) and “A Digitally Self-Calibrating 14-bit 10-MHz CMOS Pipelined A/D Converter”, IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 37, NO. 6, JUNE 2002 (hereinafter, referred to as Non-patent document 3) is a method for correcting such static properties of the analog circuit, i.e., the capacitance deviation and the DC gain of the amplifier 104 by way of processing carried out by a digital circuit. In other words, not only the analog circuit designing but also the correction by the digital circuit are used for the realization of the accuracy.
Further, even in the case where the correction is carried out with the use of the digital circuit, the analog circuit such as the pipeline AD conversion circuit is normally designed with a margin, in consideration of the device unevenness, device distortion, or the like. However, an excessive margin causes electric power consumption increase and area increase, thereby causing cost increase.
For example, the MOS transistors constituting the amplifier 112 shown in FIG. 11 inevitably have uneven threshold values in an IC chip or among IC chips, when being manufactured. For this reason, a voltage to be applied to each of the MOS transistors is an operation voltage allowing a normal operation of an MOS transistor having the highest threshold value. With this, all the MOS transistors normally operate. Such a sufficient operation voltage setting is one example of the designing with the margin. In this case, under such a sufficient operation voltage, a large amount of current is supplied to an MOS transistor having a low threshold value, and a smaller amount of current is supplied to an MOS transistor having higher threshold value. Accordingly, such a margin in the operation voltage causes electric power consumption increase in the circuit portion including the MOS transistor to which a large amount of current is supplied.
FIG. 13 illustrates a settling behavior of the output voltage Vout of each two-time amplifier circuit 111 including the amplifier 112, in the above example. Specifically, FIG. 13 illustrates how large the output voltage Vout is in a predetermined time t after the start of the hold mode during which the two-time amplifier circuit 111 outputs the output voltage. The output voltage Vout varies according to manufacturing variation of the manufactured two-time amplifiers 111. The output voltage Vout needs to be settled down to a predetermined voltage V1, in the predetermined time t1. As shown in curved lines c1 through c5, time (settling time) required for the settling to the predetermined voltage V1 in each two-time amplifier circuit 111 is changed according to a current supplied to the amplifier 112. Specifically, in the amplifier 112 to which the large current is supplied, the output voltage Vout is raised at a large through rate as shown in the curved line c1, so that the settling time is short. On the other hand, in the amplifier 112 to which the small current is supplied, the output voltage Vout is raised at a small through rate as shown in the curved line c4, so that the settling time is long. Further, in cases where the current flowing therethrough is too small, it takes more than the predetermined time t1 for the output Vout to reach the predetermined voltage V1 as shown in the curved line c5, with the result that a normal output voltage Vout cannot be obtained within the sampling interval. The margin corresponds to the length of a settlement period starting from (i) the time at which the output voltage Vout reaches the predetermined voltage V1, to (ii) the predetermined time t1. As such, the circuit designed with a large margin allows short settling time, but consumes a large electric power. Note that, this examination disregards (i) an ON-resistance of each switch, and (ii) time constant according to a parasitic component of each wire.
Further, in cases where an analog circuit having a constant settling behavior is used for an application having variable sampling speed, the settling time of the output voltage Vout is constant irrespective of the sampling speed. However, the following problem arises when the sampling time is increased. That is, the sampling time increase lengthen, by the length of the increased sampling time, the period of time starting from (i) the time at which the voltage Vout is settled, to (ii) the time at which the output voltage Vout is extracted. Therefore, the margin is unnecessarily large in the mode having such a long sampling time. For example, see a case where the sampling is carried out at such a speed that allows the output voltage Vout to reach the predetermined voltage V1 in predetermined time t2 longer than the predetermined time t1, as shown in FIG. 13. In this case, the settling behavior indicated by the curved line c5 is sufficient; however, in cases where the MOS transistor receives a current which brings the output voltage Vout to the predetermined voltage V1 in the predetermined time t1, the settlement period becomes longer by time found by “t2−t1”, as compared with the aforementioned case. As such, even when the sampling speed is changed, the current consumption of the analog circuit is constant, so that the current consumption exceeds the required amount when the sampling speed is slow.
Considered to solve the problems are: (i) preparation of a plurality of bias voltage generation circuits for respectively supplying bias voltages to amplifiers; (ii) a bias voltage generation circuit that is so arranged as to be capable of varying a voltage to be supplied therefrom; and the like. However, analog circuits are generally caused to have uneven properties when being manufactured, so that each property of analog circuits to be manufactured cannot be predicted. Therefore, even when there is provided such a bias voltage generation circuit capable of varying the output value, it is still difficult to determine a value at which the output value is set.